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Subject: Synchronous and Asynchronous Operation
Date: Sat, 1 Jan 2011 14:48:18 +0200
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<HTML><HEAD><TITLE>Synchronous and Asynchronous Operation</TITLE>
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f>
<P><BIG><BIG><BIG><STRONG>Synchronous and Asynchronous=20
Operation</STRONG></BIG></BIG></BIG></P>
<P><FONT face=3DArial>Sequential circuits are divided into two main =
types:=20
<STRONG>synchronous </STRONG>and<STRONG> asynchronous</STRONG>. Their=20
classification depends on the timing of their signals.</FONT></P>
<P><FONT face=3DArial><STRONG><EM>Synchronous </EM></STRONG>sequential =
circuits=20
change their states and output values at discrete instants of time, =
which are=20
specified by the rising and falling edge of a free-running <STRONG>clock =

signal</STRONG>. The clock signal is generally some form of square wave =
as shown=20
in Figure 2 below.</FONT></P>
<P align=3Dcenter><IMG alt=3D"clk.gif (4505 bytes)"=20
src=3D"http://www.eelab.usyd.edu.au/digital_tutorial/part3/clk.gif" =
width=3D388=20
height=3D169></P>
<P align=3Dcenter><BIG>Figure 2. Clock Signal</BIG></P>
<P align=3Dleft><FONT face=3DArial>From the diagram you can see that the =

<STRONG>clock period</STRONG> is the time between successive transitions =
in the=20
same direction, that is, between two rising or two falling edges. State=20
transitions in synchronous sequential circuits are made to take place at =
times=20
when the clock is making a transition from 0 to 1 (rising edge) or from =
1 to 0=20
(falling edge). Between successive clock pulses there is no change in =
the=20
information stored in memory.</FONT></P>
<P align=3Dleft><FONT face=3DArial>The reciprocal of the clock period is =
referred to=20
as the <STRONG>clock frequency</STRONG>. The <STRONG>clock =
width</STRONG> is=20
defined as the time during which the value of the clock signal is equal =
to 1.=20
The ratio of the clock width and clock period is referred to as the duty =
cycle.=20
A clock signal is said to be <STRONG>active high</STRONG> if the state =
changes=20
occur at the clock's rising edge or during the clock width. Otherwise, =
the clock=20
is said to be <STRONG>active low</STRONG>. Synchronous sequential =
circuits are=20
also known as <STRONG>clocked sequential circuits</STRONG>.</FONT></P>
<P><FONT face=3DArial>The memory elements used in synchronous sequential =
circuits=20
are usually flip-flops. These circuits are binary cells capable of =
storing one=20
bit of information. A flip-flop circuit has two outputs, one for the =
normal=20
value and one for the complement value of the bit stored in it. Binary=20
information can enter a flip-flop in a variety of ways, a fact which =
give rise=20
to the different types of flip-flops. For information on the different =
types of=20
basic flip-flop circuits and their logical properties, see the previous =
tutorial=20
on <A=20
href=3D"http://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop01.h=
tml">flip-flops</A>.</FONT></P>
<P><FONT face=3DArial>In <EM><STRONG>asynchronous</STRONG></EM> =
sequential=20
circuits, the transition from one state to another is initiated by the =
change in=20
the primary inputs; there is no external synchronisation. The memory =
commonly=20
used in asynchronous sequential circuits are time-delayed devices, =
usually=20
implemented by feedback among logic gates. Thus, asynchronous sequential =

circuits may be regarded as combinational circuits with feedback. =
Because of the=20
feedback among logic gates, asynchronous sequential circuits may, at =
times,=20
become unstable due to transient conditions. The instability problem =
imposes=20
many difficulties on the designer. Hence, they are not as commonly used =
as=20
synchronous systems.</FONT></P>
<P><A href=3D"javascript:loadSession('quiz2.htm')"><BIG><STRONG>Short=20
Quiz</STRONG></BIG></A></P>
<P>&nbsp;</P>
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