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Subject: Asynchronous Up-Down Counters
Date: Sat, 1 Jan 2011 15:23:29 +0200
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<HTML><HEAD><TITLE>Asynchronous Up-Down Counters</TITLE>
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<H1 align=3Dcenter><FONT color=3Dpurple><I>Asynchronous<BR>Up-Down=20
Counters</I></FONT> </H1>
<BLOCKQUOTE><B>In certain applications a counter must be able to count =
both up=20
  and down. &nbsp;The circuit below is a <FONT color=3D#0080ff>3-bit =
up-down=20
  counter</FONT>. &nbsp;It counts up or down depending on the status of =
the=20
  control signals UP and DOWN. &nbsp;When the UP input is at 1 and the =
DOWN=20
  input is at 0, the NAND network between FF0 and FF1 will gate the =
non-inverted=20
  output (Q) of FF0 into the clock input of FF1. &nbsp;Similarly, Q of =
FF1 will=20
  be gated through the other NAND network into the clock input of FF2.=20
  &nbsp;Thus the counter will count up.</B> </BLOCKQUOTE>
<P align=3Dcenter><IMG border=3D0 alt=3D"3-bit Up-Down Counter"=20
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pg"=20
width=3D511 height=3D174>=20
<BLOCKQUOTE>
  <P align=3Dleft><B>When the control input UP is at 0 and DOWN is at 1, =
the=20
  inverted outputs of FF0 and FF1 are gated into the clock inputs of FF1 =
and FF2=20
  respectively. &nbsp;If the flip-flops are initially reset to 0's, then =
the=20
  counter will go through the following sequence as input pulses are=20
  applied.</B>=20
  <P align=3Dleft>
  <TABLE cellPadding=3D2>
    <TBODY>
    <TR>
      <TD><IMG border=3D0 alt=3D"Example of an Up-Down Sequence"=20
        =
src=3D"http://www.eelab.usyd.edu.au/digital_tutorial/part2/pics/updown_ta=
b.jpg"=20
        width=3D144 height=3D156></TD>
      <TD><B>Notice that an asynchronous up-down counter is slower than =
an up=20
        counter or a down counter because of the additional propagation =
delay=20
        introduced by the NAND networks.</B></TD></TR></TBODY></TABLE>
  <P align=3Dleft><B><BR><BR><BR><BR></B></P></BLOCKQUOTE>
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