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Subject: Synchronous Up-Down Counters
Date: Sat, 1 Jan 2011 15:24:08 +0200
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>Synchronous Up-Down Counters</TITLE>
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<H1 align=3Dcenter><FONT color=3Dpurple><I>Synchronous<BR>Up-Down=20
Counters</I></FONT> </H1>
<BLOCKQUOTE><B>A circuit of a <FONT color=3D#0080ff>3-bit synchronous =
up-down=20
  counter</FONT> and a table of its sequence are shown below. =
&nbsp;Similar to=20
  an asynchronous up-down counter, a synchronous up-down counter also =
has an=20
  up-down control input. &nbsp;It is used to control the direction of =
the=20
  counter through a certain sequence.</B> </BLOCKQUOTE>
<P align=3Dcenter><IMG border=3D0 alt=3D"3-bit Synchronous Up-Down =
Counter"=20
src=3D"http://www.eelab.usyd.edu.au/digital_tutorial/part2/pics/count07.j=
pg"=20
width=3D518 height=3D174>=20
<P>
<TABLE cellPadding=3D2>
  <TBODY>
  <TR>
    <TD><IMG border=3D0 alt=3DSequence=20
      =
src=3D"http://www.eelab.usyd.edu.au/digital_tutorial/part2/pics/count07t.=
jpg"=20
      width=3D200 height=3D161></TD>
    <TD><B>An examination of the sequence table shows:</B>=20
      <UL>
        <LI><B>for both the UP and DOWN sequences, Q0 toggles on each =
clock=20
        pulse.</B>=20
        <LI><B>for the UP sequence, Q1 changes state on the next clock =
pulse=20
        when Q0=3D1.</B>=20
        <LI><B>for the DOWN sequence, Q1 changes state on the next clock =
pulse=20
        when Q0=3D0.</B>=20
        <LI><B>for the UP sequence, Q2 changes state on the next clock =
pulse=20
        when Q0=3DQ1=3D1.</B>=20
        <LI><B>for the DOWN sequence, Q2 changes state on the next clock =
pulse=20
        when Q0=3DQ1=3D0.</B> </LI></UL></TD></TR></TBODY></TABLE>
<BLOCKQUOTE><B>These characteristics are implemented with the AND, OR =
&amp;=20
  NOT logic connected as shown in the logic diagram above.</B> =
</BLOCKQUOTE>
<P><BR><BR><BR>
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