RS Flip-Flop

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## RS Flip-Flop

- A RS-flipflop is the simplest possible memory element.
- It is constructed by feeding the outputs of two NOR gates back to the other NOR gates input.
- The inputs R and S are referred to as the Reset and Set inputs, respectively.
- To understand the operation of the RS-flipflop (or RS-latch) consider the following scenarios:
  - S=1 and R=0: The output of the bottom NOR gate is equal to zero, Q'=0.
  - Hence both inputs to the top NOR gate are equal to one, thus, Q=1.
  - Hence, the input combination S=1 and R=0 leads to the flipflop being set to Q=1.
  - S=0 and R=1: Similar to the arguments above, the outputs become Q=0 and Q'=1.
  - We say that the flipflop is reset.
  - S=0 and R=0: Assume the flipflop is set (Q=0 and Q'=1), then the output of the top NOR gate remains at Q=1 and the bottom NOR gate stays at Q'=0.
  - Similarly, when the flipflop is in a reset state (Q=1 and Q'=0), it will remain there with this input combination.
  - Therefore, with inputs S=0 and R=0, the flipflop remains in its state.
  - S=1 and R=1: This input combination must be avoided.
- We can summarize the operation of the RS-flipflop by the following truth table.

  R | S | Q | Q' | Comment
  0 | 0 | Q | Q' | Hold state
  0 | 1 | 1 | 0 | Set
  1 | 0 | 0 | 1 | Reset
  1 | 1 | ? | ? | Avoid

- Note, the output Q' is simply the inverse of Q.
- An RS flipflop can also be constructed from NAND gates.

Figure 3.10: RS Flip-Flop composed of two NOR Gates.

Next: D-Flipflop Up: Memory ElementsNovember 9, 1998 Previous: Memory ElementsNovember 9, 1998