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Subject: Asynchronous (Ripple) Counters
Date: Sat, 1 Jan 2011 15:23:01 +0200
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<HTML><HEAD><TITLE>Asynchronous (Ripple) Counters</TITLE>
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<P align=3Dcenter><IMG border=3D0=20
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<H1 align=3Dcenter><FONT color=3Dpurple><I>Asynchronous<BR>(Ripple)=20
Counters</I></FONT> </H1>
<P>
<TABLE cellPadding=3D2>
  <TBODY>
  <TR>
    <TD><IMG border=3D0 alt=3D"2-bit Asynchronous Counter"=20
      =
src=3D"http://www.eelab.usyd.edu.au/digital_tutorial/part2/pics/count01.j=
pg"=20
      width=3D295 height=3D307></TD>
    <TD><B>A <FONT color=3D#0080ff>two-bit asynchronous counter =
</FONT>is shown=20
      on the left. &nbsp;The external clock is connected to the clock =
input of=20
      the first flip-flop (FF0) only. &nbsp;So, FF0 changes state at the =
falling=20
      edge of each clock pulse, but FF1 changes only when triggered by =
the=20
      falling edge of the Q output of FF0. &nbsp;Because of the inherent =

      propagation delay through a flip-flop, the transition of the input =
clock=20
      pulse and a transition of the Q output of FF0 can never occur at =
exactly=20
      the same time. &nbsp;Therefore, the flip-flops cannot be triggered =

      simultaneously, producing an asynchronous=20
operation.</B></TD></TR></TBODY></TABLE>
<BLOCKQUOTE><B>Note that for simplicity, the transitions of Q0, Q1 and =
CLK in=20
  the timing diagram above are shown as simultaneous even though this is =
an=20
  asynchronous counter. &nbsp;Actually, there is some small delay =
between the=20
  CLK, Q0 and Q1 transitions.</B> &nbsp; &nbsp;<IMG border=3D0 =
alt=3D"Count 0 to 3"=20
  align=3Dmiddle=20
  =
src=3D"http://www.eelab.usyd.edu.au/digital_tutorial/part2/pics/0-3.gif" =

  width=3D15 height=3D18>=20
  <P><B>Usually, all the CLEAR inputs are connected together, so that a =
single=20
  pulse can clear all the flip-flops before counting starts. &nbsp;The =
clock=20
  pulse fed into FF0 is rippled through the other counters after =
propagation=20
  delays, like a ripple on water, hence the name <FONT =
color=3D#0080ff>Ripple=20
  Counter</FONT>.</B>=20
  <P><B>The 2-bit ripple counter circuit&nbsp;above has four different =
states,=20
  each one corresponding to a count value. &nbsp;Similarly, a counter =
with=20
  <I>n</I> flip-flops can have <I>2 to the power n</I> states. &nbsp;The =
number=20
  of states in a counter is known as its <FONT color=3D#408080>mod =
(modulo)=20
  number</FONT>. &nbsp;Thus a 2-bit counter is a <FONT =
color=3D#408080>mod-4=20
  counter</FONT>.</B>=20
  <P><B>A mod-n counter may also described as a <FONT=20
  color=3D#0080ff>divide-by-<I>n</I> counter</FONT>. &nbsp;This is =
because the=20
  most significant flip-flop (the furthest&nbsp;flip-flop from the =
original=20
  clock pulse) produces one pulse for every <I>n</I> pulses at the clock =
input=20
  of the least significant flip-flop (the one triggers by the clock =
pulse).=20
  &nbsp;Thus, the above counter is an example of a divide-by-4 =
counter.</B>=20
  <BR><BR>
  <HR SIZE=3D4>

  <P><B>The following is a <FONT color=3D#0080ff>three-bit asynchronous =
binary=20
  counter </FONT></B><IMG border=3D0 alt=3D"Count 0 to 7"=20
  =
src=3D"http://www.eelab.usyd.edu.au/digital_tutorial/part2/pics/0-7.gif" =

  width=3D15 height=3D18> <B>and its timing diagram for one cycle. =
&nbsp;It works=20
  exactly the same way as a two-bit asynchronous binary counter =
mentioned above,=20
  except it has eight states due to the third flip-flop.</B> =
</P></BLOCKQUOTE>
<P align=3Dcenter><IMG border=3D0 alt=3D"3-bit Asynchronous Binary =
Counter"=20
src=3D"http://www.eelab.usyd.edu.au/digital_tutorial/part2/pics/count02.j=
pg"=20
width=3D396 height=3D314>=20
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